1. Field of the Invention
The present invention is related to group III-nitride field effect devices (e.g. comprising a GaN/AlGaN layer) and methods to produce an enhancement mode device of this type, i.e. a normally-off device, in which no current can flow between source and drain contact unless a positive voltage is applied to the gate.
2. Description of the Related Technology
Field effect devices of the type described above, e.g. High Electron Mobility Transistors (HEMT) comprise a two-dimensional electron gas (2 DEG) between two active layers, e.g. between an GaN layer and a AlGaN layer deposited on a Si substrate. This 2DEG layer is a consequence of piezoelectric polarization leading to charge separation within the materials. In known devices of this type, the 2DEG is present at zero gate bias due to the characteristics of the materials. GaN field effect transistor devices (FET) with contacts formed on top of the AlGaN layer are normally-on devices. The formation of contacts on the AlGaN does not change the charge polarization in the heterostructure so that if there was a 2DEG present before processing, it will remain there after formation of contacts on top of the AlGaN. A certain negative voltage, called threshold voltage, on the gate is needed to deplete the 2DEG through capacitive coupling. By applying a negative voltage to the gate, the electron channel can be pinched off. This negative voltage is typically below a negative threshold voltage (Vth), typically between −4 and −8 V. These transistors work in depletion-mode (D-mode): the channel has to be depleted to switch off the transistor.
In EP-A-1612866, a passivation layer is proposed on top of the device to solve several problems. It is intended to protect the surface of the GaN from contamination by air exposure. Furthermore, the passivation is able to stabilize the surface states of the AlGaN surface. This reduces the DC-to-RF dispersion and consequently increases the switching frequency. The passivation layer also improves the reproducibility of the device because it limits modifications of the top surface charge that influence the charge density in the 2DEG. One of the main characteristics for power switching devices in the linear operating regime is the on-state resistance. This is determined essentially by the value of the contact resistance of the Ohmic source and drain contacts, as well as by the sheet resistance of the 2DEG channel. To minimize losses, this on-state resistance should be minimal. The passivation layer mentioned in EP-A-1612866 allows for a better Ohmic contact formation. Also, a higher current density is achieved because the passivation layer on top of the AlGaN-layer has characteristics that increase the two-dimensional electron gas by introducing a higher strain in the heterostructure when compared to the device without this passivation layer.
For certain applications, such as power switching or integrated logic, a negative-polarity gate voltage supply is unwanted: the gate control of power devices in e.g. power supplies should be made similar to that used for Si devices. Field-Effect Transistors (FET) with a threshold voltage Vth=0V are normally-off devices. At zero gate voltage, no channel is present to conduct current. These transistors work in enhancement-mode (E-mode). E-mode transistors are attractive for normally-off power switches, for digital electronics applications, and for high efficiency RF applications.
To make a normally-off device, i.e. a device where no current can flow between source and drain contact when the gate is floating or grounded, one can interrupt the channel selectively under that gate contact while at the same time preserving as high as possible 2DEG density in the other regions. A positive threshold voltage will then induce 2DEG under the gate contact, allowing current to flow between source and drain. Several methods have been reported to achieve such an enhancement mode transistor:                selectively regrown p-n junction for the gate (X. Hu, G. Simin, J. Yang, M. A. Khan, R. Gaska, M. S. Shur, “Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate”, Elec. Lett. Vol. 36, No. 8, pp. 753-754, 2000),        CF4 plasma treatment of the AlxGa1−xN (Y. Cai, Y. Zhou, K. J. Chen, K. M. Lau, “High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment”, IEEE Elec. Dev. Lett. Vol. 26, No. 7, pp. 435-437, 2005)        gate recess techniques with or without post-etch RTA treatment (V. Kumar, A. Kuliev, T. Tanaka, Y. Otoki, I. Adesida, “High transconductance enhancement-mode AlGaN/GaN HEMTs on SiC substrate”, Elec. Lett. Vol. 39, No. 24, pp. 1758-1759, 2003 and W. B. Lanford, T. Tanaka, Y. Otoki, I. Adesida, “Recessed gate enhancement mode GaN HEMT with high threshold voltage”, Elec. Lett. Vol. 41, No. 7, pp. 449-450, 2005)        
In the last case, part of the AlGaN layer is selectively removed under the gate contact. As a result the remaining AlGaN is not thick enough and is not sufficiently strained relative to the GaN to create a 2DEG in between the two materials. However, a recessed gate is not a straightforward implementation. Since wet etching cannot be applied on AlxGa1−xN (no chemical etchant is known to have a significant etch rate on AlxGa1−xN), one needs to resort to dry etching techniques to remove the AlGaN (and III-nitrides in general). Plasma-assisted dry etching can be done. Dry etching of group-III nitrides is however not selective of one material composition to another. The etch rate for the typically used Cl2-based plasma is difficult to control and reproduce. The minimum etch rate obtained at the moment is around 100 nm/min, being still too high to reproducibly etch the AlxGa1−xN top layer from the 22 nm thickness to exactly 5 nm. Moreover, dry etching of group-III nitrides is known to cause an increase in the density of surface states which in their turn cause dispersion effects. Dry etching introduces a lot of defect states, resulting in a Schottky gate with high leakage current. A possible solution is an RTA anneal after the etch step. This, however, introduces yet another extra processing step, with a critical gate alignment step.